Since a switching mode power supply (SMPS) that does not employ a power factor correction circuit generates a pulse-shaped input current, high-order harmonic current flows through transmission lines, and such current does not contribute to power transmission and increases a loss in the transmission lines, transformers and the like. For this reason, the capacity of transmission lines, substations, and power stations is relatively high as compared to a case where a power factor correction circuit is used.
Accordingly, there is a movement in many countries to regulate current harmonic recently, such as EN61000-3-2, and a power factor correction circuit is used in many SMPSs in order to satisfy the regulation. The SMPS is an apparatus for converting an inputted supply voltage into one or more direct current output voltages, which is used in most home appliances such as computers, monitors, TV sets, and the like. In such an SMPS, a power factor correction circuit is used which corrects power factor by having input current follow input voltage is used. That is, the power factor correction circuit is a circuit that allows input current applied to the outside to follow input voltage and simultaneously converts an inputted alternating current (AC) voltage into a constant direct current (DC) voltage.
Such a power factor correction circuit includes an inductor, and there exists several modes depending on the state of the current flowing through the inductor. A discontinuous conduction mode refers to a case where there exists a point where the current flowing through the inductor becomes zero and thus the current is discontinuous, and a continuous conduction mode refers to a case where the current flowing through the inductor is continuous without a point where the current flowing through the inductor becomes zero. On the other hand, a critical conduction mode refers to a mode operating at a boundary point between the continuous conduction mode and the discontinuous conduction mode, in which the current flowing through the inductor increases immediately after the current flowing through the inductor becomes zero. STL6561 is the most well-known power factor correction circuit IC of the critical conduction mode, and besides this, FAN7527B, TDA4862, TDA4863, MC33260, MC33262, UC3852, SG6561, and the like are also power factor correction circuit ICs of the critical conduction mode.
FIG. 1 is a schematic circuit diagram showing a general power factor correction circuit of a critical conduction mode, and FIG. 2 is a waveform chart showing input current Iin flowing into the power factor correction circuit, current IL1 flowing through an inductor L1, voltage VAUX applied to the secondary coil NAUX of the inductor, and a gating signal inputted into a switch Qsw in the power factor correction circuit of FIG. 1. FIG. 3 is a view showing an input current waveform where a current distortion phenomenon occurs in a general power factor correction circuit shown in FIG. 1. Hereinafter, described is the operation of a general power factor correction circuit of a critical conduction mode and total harmonic distortion (THD) that occurs at this point, with reference to FIGS. 1 to 3.
Referring to FIG. 1, first, inputted alternating current voltage (AC) is full-wave rectified by a bridge diode BD, and the full-wave rectified voltage is sensed by resistors R1 and R2 and inputted into an adder 20. The sensed full-wave rectified voltage inputted into the adder 20 is multiplied by the output of an error amplifier AMP1 and inputted into the inverting terminal (−) of a comparator CMP1. On the other hand, the current flowing through the switch Qsw is sensed by a resistor Rcs, and the sensed voltage Vcs is inputted into the non-inverting terminal (+) of the comparator CMP1. The comparator CMP1 compares output of the adder 20 with output voltage of the error amplifier AMP1 and outputs a signal for turning off the switch Qsw to the reset terminal R of the flip-flop 10 at a point where the current flowing through the switch Qsw reaches a reference current outputted from the adder 20. Accordingly, the flip-flop FF turns off the switch Qsw by outputting a low signal to the output terminal Q. If the switch is turned off, the current of the inductor gradually decreases, and the time point when the current of the inductor becomes zero is sensed using the secondary coil NAUX of the inductor L1. If the time point when the current flowing through the inductor L1 becomes zero is sensed through the secondary coil NAUX, the set terminal S of the flip-flop 10 turns to a high signal, and thus the high signal is outputted to the output terminal Q. Accordingly, the switch Qsw is turned on. In this manner, the switch Qsw is turned on at the point where the current flowing through the inductor L1 becomes zero, and the switch Qsw is turned off at the point where the current flowing through the inductor L1 reaches the reference current inputted into the inverting terminal (−) of the comparator CMP1. Therefore, the input current follows the input voltage, and the power factor correction circuit operates in the critical conduction mode.
If the method described above is used, ideally, the input current should be in a sine wave, which is the same as the shape of the input voltage, by the power factor correction circuit. However, since there exits a delay time taken to sense a point where the current flowing through the inductor L1 becomes zero (hereinafter, referred to as a ero current sensing delay time?, the input current is not rendered to be in a perfect sinusoidal shape. Most of power factor correction circuits of a critical conduction mode sense a point where the current flowing through the inductor L1 becomes zero through the secondary coil NAUX of the inductor as shown in FIG. 1. However, in this case, there exists a delay time until the switch Qsw is turned on after the current IL1 of the inductor L1 becomes zero, i.e. the zero current sensing delay time, as shown in FIG. 2. When the switch Qsw is turned on, the current IL1 increases at a linear slope, and at this point, the voltage VAUX applied to the secondary coil NAUX of the inductor becomes −n*Vin (here, n denotes a turn ratio of a transformer). On the other hand, when the switch Qsw is turned off, the current IL1 decreases at a negative slope, and the voltage VAUX becomes n*(Vout−Vin). At this point, although the switch Qsw should be turned on at the point where the current IL1 becomes zero, since resonance is formed between the junction capacitor Coss of the MOSFET used as the switch Qsw and the inductor L1, the current IL1 decreases to a negative value. It is since that voltage of the capacitor Coss becomes Vout when the switch Qsw is turned off and Vout is generally set to be higher than Vin. Therefore, since electric charge charged in the capacitor Coss is discharged through the inductor L1 if the current of the inductor becomes zero and the output diode D1 is turned off, the current IL1 of the inductor decreases to a negative value. Here, the capacitor Coss connected to the switch Qsw in parallel is a junction capacitor of a MOSFET, and the diode Db is a body diode. At the point where the capacitor Coss is discharged by resonance current and thus the voltage VAUX is decreased to be lower than the reference voltage Vth, a high signal is inputted into the set terminal S of the flip-flop 10, and the switch Qsw is turned on.
Due to the operation of the zero current sensing circuit, the current of the inductor does not increase immediately after becoming zero, but increases after flowing as a negative current. Therefore, as shown in FIG. 2(a), there exists a zero current section tzero in the input current Iin of the power factor correction circuit, and thus, the average value of the input current is decreased. On the other hand, the peak value INEG of the negative current establishes the relation shown in Equation 1.
                              I          NEG                ∝                              Vout            -            Vin                                                              L                ⁢                                                                  ⁢                1                                            C                oss                                                                        [                  Equation          ⁢                                          ⁢          1                ]            
In Equation 1, Vout denotes an output voltage, and Vin denotes a full-wave rectified input voltage. As is known from Equation 1, the peak value INEG of negative current is proportional to the difference between the output voltage Vout and the input voltage Vin. Since the inductor L1 and the capacitor Coss have a fixed value and the output voltage Vout is a fixed value, the negative output current INEG is inverse proportional to the input voltage Vin. Accordingly, as the input voltage Vin is lowered, the current IL1 is further lowered to a negative value. That is, the peak value INEG of negative current is further increased at the point where the input voltage Vin passes zero voltage, and the time taken to reach the zero current from the negative current is increased when the switch is turned on again. Accordingly, zero crossing distortion occurs in the input current around the zero current as shown in FIG. 3. On the other hand, the input current shown in FIG. 3 is current before rectification.
U.S. Pat. No. 6,128,205 is a prior art for improving such distortion. U.S. Pat. No. 6,128,205 discloses a method of modifying information on rectified input voltage, which acts as a reference for turning off a switch, in order to further increase the current IL1 flowing through the inductor L1 at the point where the input voltage becomes zero. That is, the voltage applied to resistor R2 is clamped through an additional circuit and inputted into the adder 20 as shown in FIG. 1. With the rectified input voltage that is modified as described, the distortion occurring around the point where the input current becomes zero is corrected. However, such a prior art needs an additional circuit (including a plurality of resistors or the like) in order to modify the rectified input voltage and thus has a problem in that a large amount of cost is required and power is consumed by the plurality of resistors.
A method described in application note AN161 of STMicroelectronics is another conventional method, which is a method of adjusting turn-on time of a switch based on an input voltage using the second coil voltage VAUX when the switch is turned on. In this method, since the second coil voltage VAUX is proportional to the input voltage when the switch is turned on, after storing information on the input voltage in C2, a negative offset voltage ((−) Offset), which is proportional to the peak voltage of the input voltage Vin, is added to the switch current detection voltage Vcs and connected to the non-inverting terminal of the comparator CMP1. Since the voltage is increased from zero if the negative offset voltage is not added, turn-on time of the switch becomes TON—A1 in region A and TON—B1 in region B as shown in FIG. 5. However, if the negative offset voltage is added, although the switch current detection voltage Vcs is increased from the same negative voltage, the slope of the switch current detection voltage Vcs is proportional to the input voltage Vin, and thus the turn-on time increased by the negative offset voltage becomes TON—A2 in region A and TON—B2 in region B. Therefore, the time increased in region A is further larger than the time increased in region B, and thus the current distortion phenomenon is corrected by increasing the input current in region A with the turn-on time increased as such. However, this method also has a problem in that a plurality of elements is needed and thus cost is increased.
The prior arts described above are related to a circuit using a current mode control method (current mode PWM) that determines a turn-off time point of a switch by detecting current of the switch, among presently used power factor correction circuits.
Recently, frequently used is a power factor correction circuit using a voltage mode control method (voltage mode PWM) that determines a turn-off time point of a switch without detecting current of the switch as shown in FIG. 6. Since the voltage mode control method does not need information on input voltage unlike the current mode control method, an input voltage detection circuit (R1 and R2 in FIGS. 1 and 4) is not needed, and thus it is advantageous in that loss of power can be reduced.
The circuit operates in a method of generating a linearly increasing ramp signal by a ramp generator after a switch is turned on, comparing the ramp signal with the control voltage Vctrl of the output voltage controller AMP1, and turning off the switch if the ramp signal becomes equal to the control voltage Vctrl of the output voltage controller AMP1. The zero current sensing circuit and its operating method are the same as those of the power factor correction circuit of the current mode control method. If the power factor correction circuit operates as described, turn-on time of the switch does not change depending on the input voltage, but is constantly maintained as shown in FIG. 7, and power factor can be controlled.
However, the power factor correction circuit of the voltage mode control method also has the same problem of occurring distortion of input current as shown in FIG. 3 due to zero current sensing delay time.